New FPGA Tools from NI and Xilinx at NI Week 2013

New FPGA Tools from NI and Xilinx at NI Week 2013

There's plenty to love about the field-programmable gate array, or FPGA. It is essentially a customizable silicon chip that you can reprogram as many times as you want or need to in order to achieve specialized high-speed processing. In many cases, you may have a low-volume product for which an application-specific integrated circuit (ASIC) would be prohibitively expensive. An FPGA is simply a generic grid of logical units on the chip that can be interconnected programmatically, allowing you to program the logic to suit your needs.

That capability is extremely powerful. A hardware implementation of any particular algorithm is generally faster than a software implementation. FPGAs reap the speed benefits of hardware processing, but also give an engineer the ability to not only program a generic silicon die, but to reprogram it to fix bugs or improve performance. Furthermore, given enough space on the array, multiple stages of a calculation can be processed at once, either purely in parallel, or in a pipeline.

Designing the gate layout of an FPGA may seem daunting, but it is, of course, not done by hand. In fact, during NI Week 2013, National Instruments has held a number of helpful information sessions that introduce the tools available for specifying that layout. To begin, LabVIEW itself has supported FPGA programming using a subset of its G programming language since 2003. A LabVIEW programmer can simply write an algorithm using a constrained set of functions, and LabVIEW will interface with Xilinx software to produce the hardware description that will then be used to define the connections on the chip.

Due to the nature of FPGAs, however, familiar programming constructs such as loops, array operations, and floating-point operations must be used sparingly, if at all. Writing truly optimized algorithms can be tedious and error-prone, and writing un-optimized algorithms may waste a lot of gates unnecessarily, restricting the throughput and decreasing the amount of parallel processing that can be done.

One of the tools NI introduced at NI Week 2013 was the LabVIEW IP Builder, which features optimization technology from Xilinx. IP Builder provides more access to typical programming features, using smart algorithms to apply pipelining, loop-unrolling, and parallelization rules to standard LabVIEW algorithms. This way, you only need to make a few tweaks to your programming style to write an FPGA-friendly algorithm.

The rest of the optimization is achieved by specifying "directives" that tell IP Builder which optimizations you'd like to apply. On FPGAs, multiplier circuits are scarce. If you know that your algorithm needs them, but simultaneous uses are not possible, you can instruct the algorithm to use the same multiplier in several parts of the code to conserve that resource. Perhaps you know that your algorithm takes arrays as inputs, but that the entire array isn't needed all at once. Directing the hardware synthesis in this way allows IP Builder to properly allocate the FPGA's resources and increase throughput.

The crowd chimed in with a few good tips and design practices. Some optimizations due to poorly chosen directives can cause your algorithm to behave differently than intended. It was recommended that you run an un-optimized version of the FPGA code and compare it to an optimized version to ensure that the algorithm's output is as expected. This is especially true if the algorithm requires conversions from fixed-point to floating-point values. The FPGA experts agreed that IP Builder could be a valuable tool for computing polynomials, FIR filters, integrators, and the like.

Xilinx has also developed a new "system on a chip" (SoC) called Zynq, which couples two ARM processor cores with an FPGA on a single die. Zynq is featured on NI's new cRIO-9068. Combining general-purpose CPUs and a dedicated FPGA on the same chip means the parts can all easily exchange data. Certain parts of the code can be taken off the CPU, and the burden placed on the FPGA, allowing both to focus on tasks for which they are most capable, and generating significant performance improvements all around.

The significant improvement in usability and performance makes FPGAs even more attractive. We're looking forward to giving these new technologies a test drive here in the DMC offices!

DMC at NI Week 2013

NI Week 2013 Recap

Learn more about DMC's LabVIEW programming for real-time and FPGA expertise.


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NI Week 2013 Recap

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